rev. 0.14 2/06 copyright ? 2006 by silicon laboratories SI5XX-EVB SI5XX-EVB e valuation b oard for si53 x xo s and si55 x vcxo s description this document describes th e operation of the silicon laboratories SI5XX-EVB evaluation board to evaluate both silicon laboratories' si 55x vcxos and si53x xos. the si55x and si53x device s use silicon laboratories' advanced dspll ? circuitry to provide a low-jitter clock at high frequencies. the si55x/si53x ic-based device is factory configurable for a wide variety of user specifications including frequency, supply voltage, output, and tuning slope. specific configurations are factory programmed into the si55x/si53x at time of shipment, thereby eliminating the long lead times associated with cu stom oscillators. si55x/si53x samples should be ordered at the same time as the SI5XX-EVB since the evb does not come with the device. this allows end users maximum flexibility. silicon laboratories can solder down samples when ordering an evb; please specify when ordering. features ? evaluation of silicon labor atories' si55x/53x family ? ac-coupled differential output clocks ? voltage control (v c ) input port (for si55x devices) ? jumper selection for multi-frequency outputs ? jumper selection for output enable functional block diagram si5xx device v c input clk+ output bias dc block rc filter (no-pop) configuration jumpers clk? power input
SI5XX-EVB 2 rev. 0.14 1. functional description the SI5XX-EVB provides acce ss to all signals for configuring and operating the device. this board allows evaluation of the si55x vcxo device either by itself (open-loop) or within a prototype pll (closed-loop). the performance of the si53x xo device can also be evaluated on this board (the vc port is not used for xo devices). 1.1. power supply the si55x/si53x devices support operation from nominal voltages of 1.8, 2.5, and 3.3 v. review the device data sheet and part number for allowed configurations of output buffer type and device power supply. 1.2. voltage control for vcxos the voltage control (v c ) input of the si55x device is conveniently accessible through an sma jack (j3) but can also be driven (and observed) through 100 mil- centered posts (jp4). for prototyping purposes, two 0603 solder pads are located near the device v c input (r3 and c3). a traditional pll might use these as a single-time-constant low-pass filter (rc filter). the evb is shipped with a 0 resistor soldered at r3; c3 is left open. the voltage control input is not used for xo devices. 1.3. output clock because the si55x/si53x devices can support an lvpecl buffer type (in addition to lvds and cmos), pulldown resistors (r1 and r2) are available for proper output biasing. for lvpecl buffers, biasing can be achieved through a variety of equivalent circuits; the SI5XX-EVB allows for 130 pulldown resistors. after the output biasing, the high-speed outputs are dc- blocked for connection to differently biased inputs, such as standard test equipment or a phase detector evb. please review ?1.4. prep aring the evb? for non-lvpecl devices. 1.4. preparing the evb by default, the evaluation board is set up to accept lvpecl configured devices. this configuration uses 130 pull-down resistors to bias the lvpecl output stage. if an lvds, cmos, or cml based device is to be installed, the output bi asing resistors, r1 and r2, should be removed. table 1. jumper control part type jp1 jp2 jp3 jp4 si530 n/a n/a oe n/a si532 n/a n/a oe freq sel si534 freq sel1 freq sel2 oe n/a si550 n/a n/a oe v c si552 n/a n/a freq sel v c si554 freq sel1 freq sel2 oe v c notes: 1. with jumper(s) installed, signal(s) are driven low. 2. with jumper(s) not installed, signal(s) are pulled high.
SI5XX-EVB rev. 0.14 3 2. schematics vdd vdd vdd f1 oe f2 oe f2 f1 evb power input vc input high-order pole alternate vc input place in-line with j3 main output; route as differential pair silicon labs vcxo frequency select output enable jp4 jp4 j1 sma j1 sma jp1 jp1 c2 0.1uf c2 0.1uf c6 dns c6 dns j2 sma j2 sma j3 sma j3 sma c1 0.1uf c1 0.1uf c3 dns c3 dns r1 dns r1 dns c5 dns c5 dns jp2 jp2 r3 0 r3 0 pos1 1 pos2 2 j4 mkdsn 2,5/3-5,08 j4 mkdsn 2,5/3-5,08 vc 1 oe 2 clkout- 4 clkout+ 5 vdd 6 gnd 3 f1 7 f2 8 dnc 9 u1 si550 u1 si550 c4 dns c4 dns r2 dns r2 dns jp3 jp3 figure 1. SI5XX-EVB schematic
SI5XX-EVB 4 rev. 0.14 3. bill of materials item quantity reference description manufacturer's # manufacturer 1 2 c1,c2 cap,sm,0.1uf,16v,20%,x7r,0402 c0402x7r160-104kne venkel 2 2 c5 cap,sm,0.1uf,16v,20%,x7r,0603 c0603x7r160-104kne venkel 3 1 c4 cap,sm,10uf,10v,10%,tantalum,3216 ta010tcm106kar venkel 4 1 c6 cap,sm,100pf,50v,10%,c0g,0603 c0603c0g500-101kne venkel 5 4 jp1,jp2,jp3,jp4 conn,header,2x1 tsw-150-07-t-d or tsw-150-07-t-s samtec 6 3 j1,j2,j3 conn,sma side mount 901-10003 amphenol 7 1 j4 conn,power,2 position 1729018 phoenix contact 8 1 r3 res,sm,0 ohm,0603 cr0603-16w-000t venkel 9 2 r1,r2 res,sm,150,1%,0603 cr0603-16w-1500ft venkel no load 11 1 c3 cap,sm,0.1uf,16v,20%,x7r,0603 c0603x7r160-104kne venkel 10 1 u1 si5xx si5xx silicon laboratories
SI5XX-EVB rev. 0.14 5 4. layout figure 2. assembly drawing figure 3. layer 1 primary figure 4. layer 2 secondary
SI5XX-EVB 6 rev. 0.14 d ocument c hange l ist revision 0.13 to revision 0.14 ? updated "bill of materials?" on page 4. ? updated figure 2, ?assembly drawing,? on page 5.
SI5XX-EVB rev. 0.14 7 n otes :
SI5XX-EVB 8 rev. 0.14 c ontact i nformation silicon laboratories inc. 4635 boston lane austin, tx 78735 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 email: vcxoinfo@silabs.com internet: www.silabs.com silicon laboratories, silicon labs, and dspll are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and om issions, and disclaims responsibi lity for any consequences resu lting from the use of information included herein. ad ditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of t he silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmles s against all claims and damages.
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